Overview

Language

• Solaris/sparc 2.5.1 or later
• Linux/x86 with 2.2 or later kernel and glibc 6 (Redhat 6.0 or later, for example)

TauSim uses a new type of simulation algorithm to achieve higher performance than other software simulators. This "Synchronous Interpreted" algorithm computes most of the timing and sequencing behavior of a design during compilation so that only a small amount of work remains to be done during simulation. This allows TauSim to simulate approximately twice as fast as competing Verilog simulators while retaining a very fast build operation.

Every design is different, but to indicate the size and speed on a typical design we can use a complete microprocessor design by SGS-Thomsen that was entensively simulated with TauSim. The chip consists of 300,000 lines of Verilog producing 2,000,000 gates, as well as additional memory arrays.

The 24 MB memory footprint in the above table was for TauSim running in 2 state mode (0 and 1 only). TauSim can also be run in 4 state mode (0, 1, X, and Z) which increases the memory use to about 32 MB and decreases simulation speed slightly.

TauSim is different from many other Verilog simulators in that it typically simulates gate-level designs at similar speeds to RTL-level designs. This provides designers the freedom to run similar quantities of either RTL or gate-level simulations as needed.