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TauSim Language Support

TauSim supports a large and very useful subset of the IEEE 1364-1995 Verilog language:
  • Multiple clocks
  • Multiport memories
  • RTL, gate, and transistor models
  • Full set of Verilog arithmetic and logical operators
  • If else, case, casex, and casez
  • $display, $fopen, $fwrite, etc.
  • $readmemb and $readmemh
  • VCD files
  • For loops
  • Initial blocks
  • Tasks and functions
  • Basic PLI code
Questions about specific support for features can best be answered by reading the TauSim manual (a 32 page PDF, requires Acrobat Reader).


TauSim's main extension over IEEE standard Verilog is REX, providing improved accuracy X state handling. This improved X propagation helps ensure that initialization problems are detected in the RTL code, rather than later in the gate-level code.

TauSim supports the full Verilog value set of 0, 1, X, and Z. In standard Verilog, RTL "if" statements interpret X values as 0s, so the following example:

	always @ (select or d0 or d1)
		if (select)
			out = d1;
			out = d0;
will pass "d0" through to "out" if "select" is X. This is different from the behavior of a corresponding gate-level design and does not accurately model the behavior of an actual circuit. If the select input is unknown, the component could possibly propagate either of the inputs or some random value. So with REX, TauSim will set "out" to X if "select" is X.

This behavior reduces simulation mismatches between RTL and gate-level designs and allows designers to detect intialization problems during the early phases of RTL design when they are easiest to correct.

Other Extensions
TauSim includes detection of asynchronous logic and possible methodology errors during compile time. These warnings have typically indicated design problems on development projects using TauSim.

Copyright 2001 Tau Simulation