Pricing

FAQ

TauSim is highly optimized for design debugging with full performance available for any simulation. This differs from a parallel simulator, which achieves batch mode speed by simulating several test cases in parallel.

On parallel simulators, a debugging simulation may achieve only a fraction of the batch mode performance, since only a single test case is being run. A similar effect will occur whenever test cases are run serially.

With TauSim, even the gate level model for a microprocessor can run at millions of cycles per day, so lengthy serial processes such as OS boot tests can easily be run.

Comparison with Hardware Accelerators

TauSim has several advantages when compared to hardware simulation accelerators. The high performance of TauSim means many chip designs can be completed without the need for an accelerator, with greatly reduced cost and increased ease of use. For projects that require an accelerator, TauSim can be used to provide a more productive and convenient design and debugging environment.

State-of-the-art Hardware
With TauSim, simulation and build performance can easily be increased every few months by upgrading to the latest Linux systems available. Microprocessor performance is doubling every 18 months. Since TauSim is a software solution and the cost of a simulation machine is approximately $2K, it is very inexpensive to upgrade to new systems whenever more performance or capacity is desired.

With an accelerator, often the only upgrade path is to purchase a new acceleration system to replace the old one, greatly shortening the productive lifetime of the large capital investment.

Price / Performance
TauSim running on DDR-based 1 GHz or faster Linux systems provides extremely fast simulation for a fraction of the cost of an acceleration system. Design code and testbench code both run on the same machine, so even designs with substantial testbench overhead benefit from running on a "farm" of low-cost computers.

If the testbench code for a design consumes even 10% of the total simulation time, then a theoretical speedup of 9x is all that can occur even if an accelerator for design code is infinitely fast. In our experience, TauSim on the right simulation platforms provides the best price / performance ratio of any simulation solution.

Parallel Use
With TauSim, each engineer can have a dedicated simulator. This allows each designer to work independently, without competing for a shared resource.

An accelerator may only be able to run one simulation at a time. This can greatly limit the number of debugging simulations.

Low Entry Cost
A single copy of TauSim is sufficient for extensive simulation. Since significant simulation can be done for the price of one software license, the startup cost for TauSim is much lower than an accelerator.

This allows initial work on even a very large project to be done without the capital expenditure of an accelerator.

Incremental Capacity and Performance
Since TauSim can be purchased one license at a time, it is easy to buy exactly the performance that is needed and to buy additional performance over time. The capacity of TauSim is based on the memory size of the computer on which it runs. A typical Linux system can simulate a several million gate design.

The capacity and performance of an accelerator is often available only in large increments and there may be a fixed relationship between capacity and performance. It may be necessary to buy a bigger and more expensive machine than is desired, in order to get the needed performance. Or it may be necessary to buy a faster and more expensive machine than is desired, to get the needed capacity.

Low Risk
The low entry cost and high performance of TauSim allow a thorough evaluation of its capabilities before a major commitment is made. During the early stages of a new project, or the later stages of an ongoing project, a copy of TauSim can be used extensively. When the time comes to purchase a major simulation resource, getting more TauSim licenses presents extremely low risk.

An accelerator is similar to a low frequency hardware prototype. Debugging a design may be more complicated than with a simulator and may be limited to one engineer at a time. Compile times may be long and when a large amount of behavioral modeling or file I/O is done, an accelerator may only run at software speeds. These effects can limit the utility of an accelerator in some environments.